1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) switch to be used in an ATM communication network.
2. Description of the Background Art
The ATM is a well known high speed and wide bandwidth data transfer scheme in which the data are transferred in units of cells (or packets) through a network formed by transmission paths connected by ATM switches. Here, the ATM switch is a broadband ISDN communication switching device which receives each cell arriving from the input transmission line, judges the destination of each cell from its header data, and outputs each cell to an appropriate output transmission line according to the judged destination of that cell.
A conventional ATM switch has an exemplary configuration as shown in FIG. 1, in which cells arriving from input transmission lines 1101-1104 (in a case a number of input transmission lines N=4) are temporarily stored in input buffers 1301-1304, and then read out to input lines 1601-1604 of a matrix type switch 1500 formed by a plurality of crosspoints 1511-1544. Each of these crosspoints 1511-1544 of the matrix type switch 1500 is controlled by a control circuit 1050 according to the output destination data contained in the header of each cell temporarily stored in one of the input buffers 1301-1304, such that each cell read out to one of the input lines 1601-1604 is transferred appropriately by connecting said one of the input lines 1601-1604 with an appropriate one of output lines 1701-1704 of the matrix type switch 1500 at the appropriate one of the crosspoints 1511-1544. The cells transferred to the output lines 701-704 are temporarily stored in output buffers 1401-1404, and then outputted to output transmission lines 1201-1204 at respective data speeds of the output transmission lines 1201-1204.
In this conventional ATM switch of FIG. 1, the writing speed (or cell period T) at the input buffers 1301-1304 is equal to the data speed of the input transmission lines 1101-1104, and each cell is read out from each of the input buffers 1301-1304 to the matrix type switch 1500 at the speed (or internal period t) which is m times the writing speed (or cell period T) at the input buffers 1301-1304, where 1&lt;m.ltoreq.N, according to the clock signals generated by a clock signal generator 1025.
When the cell read out from the input buffer 1301 reaches to the output buffer 1404 via a route as indicated by a thick solid line in FIG. 1, for example, an acknowledge signal (ACK) is returned from this output buffer 1404 to the input buffer 1301 via the same route as the cell is transferred but in a backward direction through the acknowledge signal line 1061 as indicated by a dashed line in FIG. 1. When this acknowledge signal (ACK) is received, the input buffer 1301 stops the reading of this cell.
Here, the operation in this conventional ATM switch of FIG. 1 is carried out according to the timing chart of FIG. 2 as follows. Namely, the internal period t of the ATM switch is a period which is one m-th of the cell period T at the input buffer, and it is necessary in this ATM switch to transfer the cell from the input buffer to the output buffer and return the acknowledge signal (ACK) from that output buffer to that input buffer, both within this internal period t, in order to realize the effective arbitration. This type of the arbitration has been discloses in Japanese Patent Application Laid Open No. 1-309546 (1989).
Consequently, in the conventional ATM switch, an idle time tg is necessary after the completion of the cell transfer for the purpose of this arbitration, and this idle time tg can be unignorably long when the cell transfer speed is high.
In this regard, an ATM switch using a distributed arbitration algorithm to reduce the idle time tg has been proposed in Japanese Patent Application Laid Open No. 4-2011 (1992). In this proposition, each crosspoint has its own arbitration circuit for avoiding the conflict among cells to be outputted to the same output line. However, since there is a need for each crosspoint to negotiate the output priority with all the crosspoints connected to the same output line, a faster arbitration algorithm becomes necessary when the switch operation speed is to be further increased in order to increase the cell transmission speed. To this end, in this proposition, the acknowledge signal is returned to the input buffer from each crosspoint such that the arbitration time can be reduced compared with the aforementioned Japanese Patent Application Laid Open No, 1-309546.
However, there remains an unsolved problem concerning the further improvement of the throughput by devising simplified arbitration scheme and circuit configuration at low cost, such that the arbitration time and the blocking probability can be reduced without requiring an increase of the switch operation speed.